Omnivision examiner use only2005 china career fair exam1 logic design1.there is a fifo design which the clock of data input is running at100mhz,while the clock of data output is running at 80mhz.the inputdata is a fix pattern .800 input clocks carry in 800 datacontinuously,and the other 200 clocks carry in no data.how big the fifoshould be in order to oid data over/under_run?please select theminimum depth below to meet the requirement.A.160 b.200 c.800 d .10002.supposedly there is abinational circuit between two registersdriven by a clock.what will you do if the delay of the binationalcircuit is greater than the clock signal?a.to reduce clock frequency b.to increase clock frequencyc.to make it pipelining d to make it multi_cycle3.which of the follow circuits can generate gitch free gated_clk?a.always&emsp(posedge clk) gated =en;assign gated_clk=gated

clk;b.always&emsp(negedge clk) gated =en;assign gated_clk=gated

clk;c.always&emsp(posedge clk) gated =en;assign gated_clk=gated

clk;d.always&emsp(negedge clk) gated =en;assign gated_clk=gated

clk;4.youre working on a specification of a system with some digitalparameters.each parameter has min,typ and max columns.which columnwould you put setup and hold time?a.setup time in max,hold time in minb.setup

time in min,hold time in maxc.both in maxd.both in min5.there are 3 ants at 3corners of a triangle. They randomly startmoving towards another corner.what is the probability that wontcollide?a.0b.1/8c/1/4d.1/36.if you look at a clock and the time is 3:15.what is angle between the hour and the minute hand?a.0b.360/483.360/12d.360/47.how many times per day a clocks hands overlap?a.11b.22c.24d.268.d flip-flop :t_setup=3 ns; t_hold =1 ns; t_ck2q=1ns.what is the max clock frequency the circuit can handle?A.200mhzb.250mhzc.500mhzd.1ghz2.physical design1.before tape-out,which routine check should be performed for your layout database in 0.18 um process?a.drcb.lvsc.drcantennae.simulation2.how to fix antenna effect?a.make the wire wider and shorterb.change lower metal to upper metalc.connect with diode of metal and diffusiond.change upper metal to lower metale.bc3.please expain lvsa.logic versus schematicb.layout versus schematicc.layout via synthesisd.logic via synthesis4.how to control clock skew?a.get balanced clock treeb.decrease the fanoutc.add clock buffer evenlyd.decrease clock latency5.how to oid hold_time violation?a.lower the clock speedb.the clock arrive laterc.the clock arrive earlierd.the data arrive latere.the data arrive earlier